It is known that analog multiplier structures, such as for example the Gilbert multiplier, an embodiment of which is shown in FIG. 1, are used in the production of variable-gain stages.
This circuit is of the fully differential type and entails the application of a differential signal IN- and IN+ which is converted from a voltage to a current so that the current in output from the bridge of the Gilbert cell is constituted by a static component due to the current provided by the current source Io plus a signal component due to the differential input voltage IN- and IN+ divided by the resistance R.sub.E.
The component of the current due to the differential input voltage is due to the transconductance of the input stage composed of the bipolar transistors 1 and 2 and specifically: EQU gm=gm/(1+gm/R.sub.E)
where gm is the transconductance of transistors 1 and 2.
If now one assumes gm.R.sub.E to be much higher than 1, then gm is approximately equal to 1/R.sub.E.
A variable control voltage Vc is applied between the base of a transistor 4 and the bases of transistors 3 and 5.
By solving mathematically the appropriate circuit equations, the gain of the circuit of FIG. 1 is found to be equal to: EQU G=R.sub.L /R.sub.E.[1/(1+e.sup.Vc/Vt)]
where Vt is the threshold voltage of the transistors.
This expression can be used to show that when converting the gain into dBs by means of logarithms, in order to have gain linearity it is necessary to use a suitable control voltage Vc.
The maximum gain that can be obtained from the structure shown in FIG. 1 is in any case R.sub.L /2/R.sub.E if the control voltage Vc is equal to 0.
This entails the fact that the upper limit of the gain has a maximum value beyond which it is impossible to go; said value can be obtained by decreasing the voltage Vc to 0, i.e., if the Gilbert multiplier is balanced.
Therefore, if one wishes to provide a high gain, the ratio between R.sub.L and R.sub.E must be given a high value, by increasing the value of the load resistor R.sub.L with respect to the resistor R.sub.E. In practical terms, this entails the fact that a very large parasitic pole is generated which is determined by the product of the resistance R.sub.L and of the parasitic capacitor C, so that an increase in gain is inevitably associated with a reduction in the band, and this is a severe drawback.
Another known embodiment of a variable-gain amplifier is given in the prior documents JP 02260906A and JP 01032509A, which substantially discloses a circuit as shown in FIG. 2, in which only half of the differential circuit is shown.
Said figure illustrates a differential input stage to which a differential signal IN is fed; said differential input stage is connected to a diode (the complete differential circuit is obviously connected to a pair of diodes) Q3, whose cathode terminal is connected to the base terminal of a bipolar transistor Q4, in which the collector terminal is connected to the supply voltage by interposing a load resistor R.sub.L and the emitter terminal is connected to a current source I2.
The input signal IN is fed to a bipolar transistor Q1, whose collector terminal is connected to the cathode terminal of the diode Q3 and whose emitter terminal is connected to a resistor R.sub.E, which is in turn connected to a current source 2I.sub.1.
Parasitic capacitors C.sub.L are respectively connected between the collector terminal of the transistor Q4 and the resistor R.sub.L (parasitic capacitor C.sub.L) and between the collector terminal of the transistor Q1 and the cathode of the diode Q3 (parasitic capacitor C.sub.p).
The voltage gain can be obtained from this circuit configuration and is given by: ##EQU1##
which is obtained, as a first approximation, by ignoring the effect of the input transistor Q1.
Frequency response is instead given by the chart shown in FIG. 3, in which the first pole of the transfer function is equal to: EQU 1/R.sub.L C.sub.L.2.pi.
while the second pole is determined mainly by the contribution of the parasitic capacitor C.sub.p to the node V.sub.1, plus all the limitations determined by the transistors Q1, Q4 and Q3.